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features ? single 2.7v - 3.6v supply serial peripheral interface (spi) compatible 20 mhz max clock frequency page program operation ? single cycle reprogram (erase and program) ? 1024 pages (264 bytes/page) main memory supports page and block erase operations two 264-byte sram data buffers ? allows receiving of data while reprogramming of nonvolatile memory continuous read capability through entire array ? ideal for code shadowing applications low power dissipation ? 4 ma active read current typical ? 2 a cmos standby current typical hardware data protection feature 100% compatible to at45db021 and at45db021a 5.0v-tolerant inputs: si, sck, cs , reset and wp pins commercial and industrial temperature ranges green (pb/halide-free/rohs compliant) packaging options 1. description the at45db021b is a 2.7-volt only, serial interface flash memory ideally suited for a wide variety of digital voice-, image-, program code- and data-storage applications. its 2,162,688 bits of memory are organized as 1024 pages of 264 bytes each. in addi- tion to the main memory, the at45db021b also contains two sram data buffers of 264 bytes each. the buffers allow receiving of data while a page in the main mem- ory is being reprogrammed, as well as reading or writing a continuous data stream. eeprom emulation (bit or byte alter ability) is easily handled with a self- contained three step read-modify-write operation. unlike conventional flash memories that are accessed randomly with multiple address lines and a parallel inter- face, the dataflash uses a spi serial interface to sequentially access its data. dataflash supports spi mode 0 and mode 3. the simple serial interface facilitates hardware layout, increases system reliability, minimizes switching noise, and reduces package size and active pin count. the device is optimized for use in many commer- cial and industrial applications where high density, low pin count, low voltage, and low power are essential. the device operates at clock frequencies up to 20 mhz with a typical active read current consumption of 4 ma. to allow for simple in-system reprogra mmability, the at45db021b does not require high input voltages for programming. the device operates from a single power supply, 2.7v to 3.6v, for both the program and read operations. the at45db021b is enabled through the chip select pin (cs ) and accessed via a three-wire interface consisting of the serial input (si), serial output (so), and the serial clock (sck). all programming cycles are self-timed, and no separate erase cycle is required before programming. when the device is shipped from atmel, the most significant page of the memory array may not be erased. in other words, the contents of the last page may not be filled with ffh. 2-megabit 2.7-volt only dataflash ? at45db021b 1937j?dflsh?9/05
2 1937j?dflsh?9/05 at45db021b 2. pin configurations and pinouts table 2-1. pin configurations pin name function cs chip select sck serial clock si serial input so serial output wp hardware page write protect pin reset chip reset rdy/busy ready/busy figure 2-1. tsop top view, type 1 figure 2-2. 8-soic figure 2-3. 28-soic (1) note: 1. this package is not recommended for new designs. figure 2-4. cbga top view through package 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 rdy/busy reset wp nc nc vcc gnd nc nc nc cs sck si so nc nc nc nc nc nc nc nc nc nc nc nc nc nc 1 2 3 4 8 7 6 5 si sck reset cs so gnd vcc wp 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 gnd nc nc cs sck si so nc nc nc nc nc nc nc vcc nc nc wp reset rdy/busy nc nc nc nc nc nc nc nc a b c 123 vcc wp reset gnd rdy/bsy si sck cs so
3 1937j?dflsh?9/05 at45db021b 3. block diagram 4. memory array to provide optimal flexibility, the memory array of the at45db021b is divided into three levels of granularity comprised of sectors, blocks and pages. the memory architecture diagram illus- trates the breakdown of each level and details the number of pages per sector and block. all program operations to the dataflash occur on a page-by-page basis; however, the optional erase operations can be performed at the block or page level. figure 4-1. memory architecture diagram flash memory array page (264 bytes) buffer 2 (264 bytes) buffer 1 (264 bytes) i/o interface sck cs reset vcc gnd rdy/busy wp so si sector 0a = 8 pages 2112 bytes (2k + 64) sector 0b = 248 pages 65,472 bytes (62k + 1984) block = 2112 bytes (2k + 64) 8 pages sector 0 sector 1 page = 264 bytes (256 + 8) page 0 page 1 page 6 page 7 page 8 page 9 page 1022 page 1023 block 0 page 14 page 15 page 16 page 17 page 18 page 1021 block 1 sector architecture block architecture page architecture block 0 block 1 block 30 block 31 block 32 block 33 block 126 block 127 block 62 block 63 block 64 block 65 sector 2 block 2 sector 0c = 256 pages 67,584 bytes (64k + 2k) sector 1 = 512 pages 135,168 bytes (128k + 4k)
4 1937j?dflsh?9/05 at45db021b 5. device operation the device operation is controlled by instructions from the host processor. the list of instructions and their associated opcodes are contained in tables 1 through 4 (pages 9 and 11 ). a valid instruction starts with the falling edge of cs followed by the appropriate 8-bit opcode and the desired buffer or main memory address location. while the cs pin is low, toggling the sck pin controls the loading of the opcode and the desired buffer or main memory address location through the si (serial input) pin. all instructions, addresses, and data are transferred with the most significant bit (msb) first. buffer addressing is referenced in the datasheet using the terminology bfa8-bfa0 to denote the nine address bits required to designate a byte address within a buffer. main memory addressing is referenced using the terminology pa9-pa0 and ba8-ba0 where pa9-pa0 denotes the 10 address bits required to designate a page address and ba8-ba0 denotes the nine address bits required to designate a byte address within the page. 5.1 read commands by specifying the appropriate opcode, data can be read from the main memory or from either one of the two data buffers. the dataflash supports two categories of read modes in relation to the sck signal. the differences between the modes are in respect to the inactive state of the sck signal as well as which clock cycle data will begin to be output. the two categories, which are comprised of four modes total, are defined as inactive clock polarity low or inactive clock polarity high and spi mode 0 or spi mode 3. a separate opcode (refer to table 5-3 on page 9 for a complete list) is used to select which category will be used for reading. please refer to the ?detailed bit-level read timing? diagrams in this datasheet for details on the clock cycle sequences for each mode. 5.1.1 continuous array read by supplying an initial starting address for the main memory array, the continuous array read command can be utilized to sequentially read a continuous stream of data from the device by simply providing a clock signal; no additional addressing information or control signals need to be provided. the dataflash inco rporates an inter nal address counter t hat will automatically increment on every clock cycle, allowing one continuous read operation without the need of additional address sequences. to perform a continuous read, an opcode of 68h or e8h must be clocked into the device followed by 24 address bits and 32 don?t care bits. the first five bits of the 24-bit address sequence are reserved for upward and downward compatibility to larger and smaller density devices (see notes under ?command sequence for read/write operations? dia- gram). the next 10 address bits (pa9-pa0) specify which page of the main memory array to read, and the last nine bits (ba8-ba0) of the 24-bit address sequence specify the starting byte address within the page. the 32 don?t care bits that follow the 24 address bits are needed to ini- tialize the read operation. following the 32 don? t care bits, additional clock pulses on the sck pin will result in serial data being output on the so (serial output) pin. the cs pin must remain low during the loading of the opcode, the address bits, the don?t care bits, and the reading of data. when the end of a page in main memory is reached during a con- tinuous array read, the device will continue reading at the beginning of the next page with no delays incurred during the page boundary crossover (the crossover from the end of one page to the beginning of the next page). when the last bit in the main memory array has been read, the device will continue reading back at the beginning of the first page of memory. as with crossing over page boundaries, no delays will be incurred when wrapping around from the end of the array to the beginning of the array.
5 1937j?dflsh?9/05 at45db021b a low-to-high transition on the cs pin will terminate the read operation and tri-state the so pin. the maximum sck frequency allowable for the c ontinuous array read is defined by the f car specification. the continuous array read bypasses both data buffers and leaves the contents of the buffers unchanged. 5.1.2 main memory page read a main memory page read allows the user to read data directly from any one of the 1024 pages in the main memory, bypassing both of the data buffers and leaving the contents of the buffers unchanged. to start a page read, an opcode of 52h or d2h must be clocked into the device fol- lowed by 24 address bits and 32 don?t care bits. the first five bits of the 24-bit address sequence are reserved bits, the next 10 address bits ( pa9-pa0) specify the page address, and the next nine address bits (ba8-ba0) specify the starting byte address within the page. the 32 don?t care bits which follow the 24 address bits are sent to initialize the read operation. following the 32 don?t care bits, additional pulses on sck result in serial data being output on the so (serial output) pin. the cs pin must remain low during the loading of the opcode, the address bits, the don?t care bits and the reading of data. when the end of a page in main memory is reached dur- ing a main memory page read, the device wi ll continue reading at the beginning of the same page. a low-to-high transition on the cs pin will terminate the read operation and tri-state the so pin. 5.1.3 buffer read data can be read from either one of the two buffers, using different opcodes to specify which buffer to read from. an opcode of 54h or d4h is used to read data from buffer 1, and an opcode of 56h or d6h is used to read data from buffer 2. to perform a buffer read, the eight bits of the opcode must be followed by 15 don?t care bits, nine address bits, and eight don?t care bits. since the buffer size is 264-bytes, nine address bits (bfa8-bfa0) are required to specify the first byte of data to be read from the buffer. the cs pin must remain low during the loading of the opcode, the address bits, the don?t care bits and the reading of data. when the end of a buffer is reached, the device will continue reading back at the begi nning of the buffer. a low-to-high transition on the cs pin will terminate the read operation and tri-state the so pin. 5.1.4 status register read the status register can be used to determine the device?s ready/busy status, the result of a main memory page to buffer compare operation, or the device density. to read the status register, an opcode of 57h or d7h must be loaded into the device. after the last bit of the opcode is shifted in, the eight bits of the status register, starting with the msb (bit 7), will be shifted out on the so pin during the next eight clock cycles. the five most-significant bits of the status register will contain device information, while the remainin g three least-si gnificant bits are reserved for future use and will have undefined values. after bit 0 of the status register has been shifted out, the sequence will repeat itself (as long as cs remains low and sck is being toggled) starting again with bit 7. the data in the status register is constantly updated, so each repeating sequence will output new data. ready/busy status is indicated using bit 7 of the status register. if bit 7 is a 1, then the device is not busy and is ready to accept the next command. if bit 7 is a 0, then the device is in a busy state. the user can continuously poll bit 7 of the status register by stopping sck at a low level table 5-1. status register format bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rdy/busy comp0101xx
6 1937j?dflsh?9/05 at45db021b once bit 7 has been output. the status of bit 7 will continue to be output on the so pin, and once the device is no longer busy, the state of so will change from 0 to 1. there are eight operations that can cause the device to be in a busy state: main memory page to buffer transfer, main memory page to buffer compare, buffer to main memory page program with built-in erase, buffer to main memory page program without built-in erase, page erase, block erase, main memory page program, and auto page rewrite. the result of the most recent main memory page to buffer compare operation is indicated using bit 6 of the status register. if bit 6 is a 0, then the data in the main memory page matches the data in the buffer. if bit 6 is a 1, then at least one bit of the data in the main memory page does not match the data in the buffer. the device density is indicated using bits 5, 4, 3 and 2 of the status register. for the at45db021b, the four bits are 0, 1, 0 and 1. t he decimal value of these four binary bits does not equate to the device density; the four bits represent a combinational code relating to differing densities of serial dataflash devices, allowing a total of sixteen different density configurations. 5.2 program and erase commands 5.2.1 buffer write data can be shifted in from the si pin into either buffer 1 or buffer 2. to load data into either buffer, an 8-bit opcode, 84h for buffer 1 or 87h for buffer 2, must be followed by 15 don't care bits and nine address bits (bfa8-bfa0). the nine address bits specify the first byte in the buffer to be written. the data is entered following the address bits. if the end of the data buffer is reached, the device will wrap around back to the beginning of the buffer. data will continue to be loaded into the buffer until a low-to-high transition is detected on the cs pin. 5.2.2 buffer to main memory page program with built-in erase data written into either buffer 1 or buffer 2 can be programmed into the main memory. to start the operation, an 8-bit opcode (83h for buffer 1 or 86h for buffer 2) must be followed by the five reserved bits, 10 address bits (pa9-pa0) that specify the page in the main memory to be writ- ten, and nine additional don?t care bits. when a low-to-high transition occurs on the cs pin, the part will first erase the selected page in main memory to all 1s and then program the data stored in the buffer into the specified page in the main memory. both the erase and the programming of the page are internally self-timed and should take place in a maximum time of t ep . during this time, the status register will indicate that the part is busy. 5.2.3 buffer to main memory page program without built-in erase a previously erased page within main memory can be programmed with the contents of either buffer 1 or buffer 2. to start the operation, an 8-bit opcode (88h for buffer 1 or 89h for buffer 2) must be followed by the five reserved bits, 10 address bits (pa9-pa0) that specify the page in the main memory to be written, and nine additional don?t care bits. when a low-to-high transition occurs on the cs pin, the part will program the data stored in the buffer into the specified page in the main memory. it is necessary that the page in main memory that is being programmed has been previously erased. the programming of t he page is internally self-timed and should take place in a maximum time of t p . during this time, the status register will indicate that the part is busy. successive page programming operations without doing a page erase are not recommended. in other words, changing bytes within a page from a ?1? to a ?0? during multiple page programming operations without erasing that page is not recommended.
7 1937j?dflsh?9/05 at45db021b 5.2.4 page erase the optional page erase command can be used to individually erase any page in the main memory array allowing the buffer to main memory page program without built-in erase com- mand to be utilized at a later time. to perform a page erase, an opcode of 81h must be loaded into the device, followed by five reserved bits, ten address bits (pa9-pa0), and nine don?t care bits. the ten address bits are used to specify which page of the memory array is to be erased. when a low-to-high transition occurs on the cs pin, the part will erase the selected page to 1s. the erase operation is internally self-timed and should take place in a maximum time of t pe . dur- ing this time, the status register will indicate that the part is busy. 5.2.5 block erase a block of eight pages can be erased at one time allowing the buffer to main memory page pro- gram without built-in erase command to be utilized to reduce programming times when writing large amounts of data to the device. to perform a block erase, an opcode of 50h must be loaded into the device, followed by five reserved bits, seven address bits (pa9-pa3), and 12 don?t care bits. the seven address bits are used to specify which block of eight pages is to be erased. when a low-to-high transition occurs on the cs pin, the part will erase the selected block of eight pages to 1s. the erase operation is internally self-timed and should take place in a maximum time of t be . during this time, the status register will indicate that the part is busy. 5.2.6 main memory page program through buffer this operation is a combination of the buffer write and buffer to main memory page program with built-in erase operations. data is first shifted into buffer 1 or buffer 2 from the si pin and then programmed into a specified page in the main memory. to initiate the operation, an 8-bit opcode (82h for buffer 1 or 85h for buffer 2) must be followed by the five reserved bits and 20 address bits. the 10 most-significant address bits (pa9-pa0) select the page in the main mem- ory where data is to be written, and the next nine address bits (bfa8-bfa0) select the first byte in the buffer to be written. after all address bits are shifted in, the part will take data from the si pin and store it in one of the data buffers. if the end of the buffer is reached, the device will wrap around back to the beginning of the buffer. when there is a low-to-high transition on the cs pin, the part will first erase the selected page in main memory to all 1s and then program the data stored in the buffer into the specified page in the main memory. both the erase and the program- ming of the page are internally self-timed and should take place in a maximum of time t ep . during this time, the status register will indicate that the part is busy. table 5-2. block erase addressing pa9 pa8 pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 block 0000000xxx 0 0000001xxx 1 0000010xxx 2 0000011xxx 3 1111100xxx124 1111101xxx125 1111110xxx126 1111111xxx127
8 1937j?dflsh?9/05 at45db021b 5.3 additional commands 5.3.1 main memory page to buffer transfer a page of data can be transferred from the main memory to either buffer 1 or buffer 2. to start the operation, an 8-bit opcode, 53h for buffer 1 and 55h for buffer 2, must be followed by the five reserved bits, 10 address bits (pa9-pa0) which specify the page in main memory that is to be transferred, and nine don?t care bits. the cs pin must be low while toggling the sck pin to load the opcode, the address bits, and the don?t care bits from the si pin. the transfer of the page of data from the main memory to the buffer will begin when the cs pin transitions from a low to a high state. during the transfer of a page of data (t xfr ), the status register can be read to determine whether the transfer has been completed or not. 5.3.2 main memory page to buffer compare a page of data in main memory can be compared to the data in buffer 1 or buffer 2. to initiate the operation, an 8-bit opcode (60h for buffer 1 and 61h for buffer 2) must be followed by 24 address bits consisting of the five reserved bi ts, 10 address bits (pa9-pa0) which specify the page in the main memory that is to be compared to the buffer, and nine don?t care bits. the cs pin must be low while toggling the sck pin to load the opcode, the address bits and the don?t care bits from the si pin. on the low-to-high transition of the cs pin, the 264 bytes in the selected main memory page will be compared with the 264 bytes in buffer 1 or buffer 2. during this time (t xfr ), the status register will indicate that the part is busy. on completion of the com- pare operation, bit 6 of the status register is updated with the result of the compare. 5.3.3 auto page rewrite this mode is needed only if multiple bytes within a page or multiple pages of data are modified in a random fashion. this mode is a combination of two operations: main memory page to buffer transfer and buffer to main memory page program with built-in erase. a page of data is first transferred from the main memory to buffer 1 or buffer 2, and then the same data (from buffer 1 or buffer 2) is programmed back into its original page of main memory. to start the rewrite oper- ation, an 8-bit opcode (58h for buffer 1 or 59h for buffer 2) must be followed by the five reserved bits, 10 address bits (pa9-pa0) that specify the page in main memory to be rewritten, and nine additional don?t care bits. when a low-to-high transition occurs on the cs pin, the part will first transfer data from the page in main memory to a buffer and then program the data from the buffer back into same page of main memory. the operation is internally self-timed and should take place in a maximum time of t ep . during this time, the status register will indicate that the part is busy. if a sector is programmed or reprogrammed sequentially page-by-page, then the programming algorithm shown in figure 15-1 on page 25 is recommended. otherwise, if multiple bytes in a page or several pages are programmed randomly in a sector, then the programming algorithm shown in figure 15-2 on page 26 is recommended. each page within a sector must be updated/rewritten at least once within every 10,000 cumulative page erase/program operations in that sector.
9 1937j?dflsh?9/05 at45db021b 5.4 operation mode summary the modes described can be separated into two groups ? modes which make use of the flash memory array (group a) and modes which do not make use of the flash memory array (group b). group a modes consist of: 1. main memory page read 2. main memory page to buffer 1 (or 2) transfer 3. main memory page to buffer 1 (or 2) compare 4. buffer 1 (or 2) to main memory page program with built-in erase 5. buffer 1 (or 2) to main memory page program without built-in erase 6. page erase 7. block erase 8. main memory page program through buffer 9. auto page rewrite group b modes consist of: 1. buffer 1 (or 2) read 2. buffer 1 (or 2) write 3. status register read if a group a mode is in progress (not fully completed), then another mode in group a should not be started. however, during this time in which a group a mode is in progress, modes in group b can be started. this gives the serial dataflash the ability to virtually accommodate a continuous data stream. while data is being programmed into main memory from buffer 1, data can be loaded into buffer 2 (or vice versa). see application note an-4 (?using atmel?s serial dataflash?) for more details. table 5-3. read commands command sck mode opcode continuous array read inactive clock polarity low or high 68h spi mode 0 or 3 e8h main memory page read inactive clock polarity low or high 52h spi mode 0 or 3 d2h buffer 1 read inactive clock polarity low or high 54h spi mode 0 or 3 d4h buffer 2 read inactive clock polarity low or high 56h spi mode 0 or 3 d6h status register read inactive clock polarity low or high 57h spi mode 0 or 3 d7h
10 1937j?dflsh?9/05 at45db021b note: in tables 2 and 3, an sck mode designation of ?any? denotes any one of the four modes of operation (inactive clock polarit y low, inactive clock polarity high, spi mode 0, or spi mode 3). table 5-4. program and erase commands command sck mode opcode buffer 1 write any 84h buffer 2 write any 87h buffer 1 to main memory page program with built-in erase any 83h buffer 2 to main memory page program with built-in erase any 86h buffer 1 to main memory page program without built-in erase any 88h buffer 2 to main memory page program without built-in erase any 89h page erase any 81h block erase any 50h main memory page program through buffer 1 any 82h main memory page program through buffer 2 any 85h table 5-5. additional commands command sck mode opcode main memory page to buffer 1 transfer any 53h main memory page to buffer 2 transfer any 55h main memory page to buffer 1 compare any 60h main memory page to buffer 2 compare any 61h auto page rewrite through buffer 1 any 58h auto page rewrite through buffer 2 any 59h
11 1937j?dflsh?9/05 at45db021b note: r = reserved bit p = page address bit b = byte/buffer address bit x = don?t care table 5-6. detailed bit-level addressing sequence opcode opcode address byte address byte address byte additional don?t care bytes required 50h 01010000r r r r r ppppppp xxxxxxxxxxxx n/a 52h 01010010r r r r r pppppppppp bbbbbbbbb 4 bytes 53h 01010011r r r r r pppppppppp xxxxxxxxx n/a 54h 01010100x x xxxxxxxxxxxxx bbbbbbbbb 1 byte 55h 01010101r r r r r pppppppppp xxxxxxxxx n/a 56h 01010110x x xxxxxxxxxxxxx bbbbbbbbb 1 byte 57h 01010111 n/a n/a n/a n/a 58h 01011000r r r r r pppppppppp xxxxxxxxx n/a 59h 01011001r r r r r pppppppppp xxxxxxxxx n/a 60h 01100000r r r r r pppppppppp xxxxxxxxx n/a 61h 01100001r r r r r pppppppppp xxxxxxxxx n/a 68h 01101000r r r r r pppppppppp bbbbbbbbb 4 bytes 81h 10000001r r r r r pppppppppp xxxxxxxxx n/a 82h 10000010r r r r r pppppppppp bbbbbbbbb n/a 83h 10000011r r r r r pppppppppp xxxxxxxxx n/a 84h 10000100x x xxxxxxxxxxxxx bbbbbbbbb n/a 85h 10000101r r r r r pppppppppp bbbbbbbbb n/a 86h 10000110r r r r r pppppppppp xxxxxxxxx n/a 87h 10000111x x xxxxxxxxxxxxx bbbbbbbbb n/a 88h 10001000r r r r r pppppppppp xxxxxxxxx n/a 89h 10001001r r r r r pppppppppp xxxxxxxxx n/a d2h 11010010r r r r r pppppppppp bbbbbbbbb 4 bytes d4h 11010100x x xxxxxxxxxxxxx bbbbbbbbb 1 byte d6h 11010110x x xxxxxxxxxxxxx bbbbbbbbb 1 byte d7h 11010111 n/a n/a n/a n/a e8h 11101000r r r r r pppppppppp bbbbbbbbb 4 bytes r eserve d reserved reserved r eserve d r eserve d pa 9 pa 8 pa 7 pa 6 pa 5 pa 4 pa 3 pa2 pa1 pa 0 ba 8 ba 7 ba 6 ba 5 ba 4 ba 3 ba 2 ba 1 ba0
12 1937j?dflsh?9/05 at45db021b 5.5 pin descriptions serial input (si): the si pin is an input-only pin and is used to shift data into the device. the si pin is used for all data input, including opcodes and address sequences. serial output (so): the so pin is an output-only pin and is used to shift data out from the device. serial clock (sck): the sck pin is an input-only pin and is used to control the flow of data to and from the dataflash. data is always clocked into the device on the rising edge of sck and clocked out of the device on the falling edge of sck. chip select (cs ): the dataflash is selected when the cs pin is low. when the device is not selected, data will not be accepted on the si pin, and the so pin will remain in a high-impedance state. a high-to-low transition on the cs pin is required to start an operation, and a low-to-high transition on the cs pin is required to end an operation. write protect: if the wp pin is held low, the first 256 pages of the main memory cannot be reprogrammed. the only way to reprogram the first 256 pages is to first drive the protect pin high and then use the program commands previously m entioned. if this pin and feature are not uti- lized it is recommended that the wp pin be driven high externally. reset : a low state on the reset pin (reset ) will terminate the operation in progress and reset the internal state machine to an idle state. the device will remain in the reset condition as long as a low level is present on the reset pin. normal operation can resume once the reset pin is brought back to a high level. the device incorporates an internal power-on reset circuit, so there are no restrictions on the reset pin during power-on sequences. if this pin and feature are not utilized it is recommended that the reset pin be driven high externally. ready/busy : this open-drain output pin will be driven low when the device is busy in an inter- nally self-timed operation. this pin, which is normally in a high state (through a 1k ? external pull-up resistor), will be pulled low during programming operations, compare operations, and during page-to-buffer transfers. the busy status indicates that the flash memory array and one of the buffers cannot be accessed; read and write operations to the other buffer can still be performed. 6. power-on/reset state when power is first applied to the device, or when recovering from a reset condition, the device will default to spi mode 3. in addition, the so pin will be in a high-impedance state, and a high- to-low transition on the cs pin will be required to start a valid instruction. the spi mode will be automatically selected on every falling edge of cs by sampling the inactive clock state. after power is applied and v cc is at the minimum datasheet value, the system should wait 20 ms before an operational mode is started.
13 1937j?dflsh?9/05 at45db021b note: 1. after power is applied and v cc is at the minimum specified datasheet value, the system should wait 20 ms before an operational mode is started. note: 1. i cc1 during a buffer read is 20ma maximum. 7. absolute maximum ratings* temperature under bias ................................ -55 c to +125 c *notice: stresses beyond those listed under ?absolute maximum ratings? may cause permanent dam- age to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. storage temperature ..................................... -65 c to +150 c all input voltages (including nc pins) with respect to ground ...................................-0.6v to +6.25v all output voltages with respect to ground .............................-0.6v to v cc + 0.6v 8. dc and ac operating range at45db021b operating temperature (case) com. 0 c to 70 c ind. -40 c to 85 c v cc power supply (1) 2.7v to 3.6v 8.1 dc characteristics symbol parameter condition min typ max units i sb standby current cs , reset , wp = v cc , all inputs at cmos levels 210a i cc1 (1) active current, read operation f = 15 mhz; i out = 0 ma; v cc = 3.6v 410ma i cc2 active current, program/erase operation v cc = 3.6v 15 35 ma i li input load current v in = cmos levels 1 a i lo output leakage current v i/o = cmos levels 1 a v il input low voltage 0.6 v v ih input high voltage 2.0 v v ol output low voltage i ol = 1.6 ma; v cc = 2.7v 0.4 v v oh output high voltage i oh = -100 a v cc - 0.2v v
14 1937j?dflsh?9/05 at45db021b 8.3 input test waveforms and measurem ent levels t r , t f < 3 ns (10% to 90%) 8.4 output test load 8.2 ac characteristics symbol parameter min max units f sck sck frequency 20 mhz f car sck frequency for continuous array read 20 mhz t wh sck high time 22 ns t wl sck low time 22 ns t cs minimum cs high time 250 ns t css cs setup time 250 ns t csh cs hold time 250 ns t csb cs high to rdy/busy low 200 ns t su data in setup time 5 ns t h data in hold time 10 ns t ho output hold time 0 ns t dis output disable time 18 ns t v output valid 20 ns t xfr page to buffer transfer/compare time 250 s t ep page erase and programming time 20 ms t p page programming time 14 ms t pe page erase time 8ms t be block erase time 12 ms t rst reset pulse width 10 s t rec reset recovery time 1 s ac driving levels ac measurement level 0.45v 2.0 0.8 2.4v device under test 30 pf
15 1937j?dflsh?9/05 at45db021b 9. ac waveforms two different timing diagrams are shown below . waveform 1 shows the sck signal being low when cs makes a high-to-low transition, and waveform 2 shows the sck signal being high when cs makes a high-to-low transition. both waveforms show valid timing diagrams. the setup and hold times for the si signal are referenced to the low-to-high transition on the sck signal. waveform 1 shows timing that is also compatible with spi mode 0, and waveform 2 shows tim- ing that is compatible with spi mode 3. 9.1 waveform 1 ? inactive clock polarity low and spi mode 0 9.2 waveform 2 ? inactive clock polarity high and spi mode 3 cs sck si so t css valid in t h t su t wh t wl t csh t cs t v high impedance valid out t ho t dis high impedance cs sck si so t css valid in t h t su t wl t wh t csh t cs t v high z valid out t ho t dis high impedance
16 1937j?dflsh?9/05 at45db021b 9.3 reset timing (inactive clock polarity low shown) note: the cs signal should be in the high state before the reset signal is deasserted. 9.4 command sequence for read/write operat ions (except status register read) notes: 1. ?r? designates bits reserved for larger densities. 2. it is recommended that ?r? be a logical ?0? for densities of 2m bits or smaller. 3. for densities larger than 2m bits, the ?r? bits become the most significant page address bit for the appropriate density. cs sck reset so high impedance high impedance si t rst t rec t css si cmd 8 bits 8 bits 8 bits msb reserved for larger densities page address (pa9-pa0) byte/buffer address (ba8-ba0/bfa8-bfa0) lsb r r r r r x x x x x x x x x x x x x x x x x x x
17 1937j?dflsh?9/05 at45db021b 10. write operations the following block diagram and waveforms illustrate the various write sequences available. 10.1 main memory page program through buffers 10.2 buffer write 10.3 buffer to main memory page program (data from buffer programmed into flash page) flash memory array page (256 bytes) buffer 2 (256 bytes) buffer 1 (256 bytes) i/o interface si buffer 1 to page program page program through buffer 2 buffer 2 to page program page program through buffer 1 buffer 1 write buffer 2 write si cmd n n+1 last byte completes writing into selected buffer starts self-timed erase/program operation cs rrrr r, pa9-7 pa6-0, bfa8 bfa7-0 si cmd x xx, bfa8 bfa7-0 n n+1 last byte completes writing into selected buffer cs si cmd rrrr r, pa9-7 pa6-0, x cs starts self-timed erase/program operation x each transition represents 8 bits and 8 clock c y cles n = 1st byte read n+1 = 2nd byte read
18 1937j?dflsh?9/05 at45db021b 11. read operations the following block diagram and waveforms illustrate the various read sequences available. 11.1 main memory page read 11.2 main memory page to buffer transfer (data from flash page read into buffer) 11.3 buffer read flash memory array page (264 bytes) buffer 2 (264 bytes) buffer 1 (264 bytes) i/o interface main memory page to buffer 1 main memory page to buffer 2 main memory page read buffer 1 read buffer 2 read so si cmd rrrr r, pa9-7 pa6-0, ba8 ba7-0 x xxx cs n n+1 so si cmd rrrr r, pa9-7 pa6-0, x x starts reading page data into buffer cs so si cmd x xx, bfa8 bfa7-0 cs n n+1 so x each transition represents 8 bits and 8 clock c y cles n = 1st byte read n+1 = 2nd byte read
19 1937j?dflsh?9/05 at45db021b 12. detailed bit-level read timing ? inactive clock polarity low 12.1 continuous array read (opcode: 68h) 12.2 main memory page read (opcode: 52h) si 0 1xx cs so sck 12 63 64 65 66 67 68 high-impedance d 7 d 6 d 5 d 2 d 1 d 0 d 7 d 6 d 5 data out bit 0 of page n+1 bit 2111 of page n lsb msb t su t v si 0 1 0 10 xxx cs so sck 12345 60 61 62 63 64 65 66 67 xx high-impedance d 7 d 6 d 5 data out command opcode msb t su t v
20 1937j?dflsh?9/05 at45db021b 12.3 buffer read (o pcode: 54h or 56h) 12.4 status register read (opcode: 57h) si 0 1 0 10 xxx cs so sck 12345 36 37 38 39 40 41 42 43 xx high-impedance d 7 d 6 d 5 data out command opcode msb t su t v si 0 1 0 10 111 cs so sck 12345 78910 11 12 16 17 high-impedance d 7 d 6 d 5 status register output command opcode msb t su t v 6 d 1 d 0 d 7 lsb msb
21 1937j?dflsh?9/05 at45db021b 13. detailed bit-level read timing ? inactive clock polarity high 13.1 continuous array read (opcode: 68h) 13.2 main memory page read (opcode: 52h) 13.3 buffer read (o pcode: 54h or 56h) si 0 1xxx cs so sck 12 63 64 65 66 67 high-impedance d 7 d 6 d 5 d 2 d 1 d 0 d 7 d 6 d 5 bit 0 of page n+1 bit 2111 of page n lsb msb t su t v data out si 0 1 0 10 xxx cs so sck 12345 61 62 63 64 65 66 67 xx high-impedance d 7 d 6 d 5 data out command opcode msb t su t v d 4 68 si 0 1 0 10 xxx cs so sck 12345 37 38 39 40 41 42 43 xx high-impedance d 7 d 6 d 5 data out command opcode msb t su t v d 4 44
22 1937j?dflsh?9/05 at45db021b 13.4 status register read (opcode: 57h) 14. detailed bit-level read timing ? spi mode 0 14.1 continuous array read (opcode: e8h) 14.2 main memory page read (opcode: d2h) si 0 1 0 10 111 cs so sck 12345 78910 11 12 17 18 high-impedance d 7 d 6 d 5 status register output command opcode msb t su t v 6 d 4 d 0 d 7 lsb msb d 6 si 1 1xxx cs so sck 12 62 63 64 65 66 67 high-impedance d 7 d 6 d 5 d 2 d 1 d 0 d 7 d 6 d 5 data out bit 0 of page n+1 bit 2111 of page n lsb msb t su t v si 1 1 0 10 xxx cs so sck 12345 60 61 62 63 64 65 66 67 xx high-impedance d 7 d 6 d 5 data out command opcode msb t su t v d 4
23 1937j?dflsh?9/05 at45db021b 14.3 buffer read (opcode: d4h or d6h) 14.4 status register read (opcode: d7h) 15. detailed bit-level read timing ? spi mode 3 15.1 continuous array read (opcode: e8h) si 1 1 0 10 xxx cs so sck 12345 36 37 38 39 40 41 42 43 xx high-impedance command opcode t su d 7 d 6 d 5 data out msb t v d 4 si 1 1 0 10 111 cs so sck 12345 78910 11 12 16 17 high-impedance status register output command opcode msb t su 6 d 1 d 0 d 7 lsb msb d 7 d 6 d 5 t v d 4 si 1 1xxx cs so sck 12 63 64 65 66 67 high-impedance d 7 d 6 d 5 d 2 d 1 d 0 d 7 d 6 d 5 bit 0 of page n+1 bit 2111 of page n lsb msb t su t v data out
24 1937j?dflsh?9/05 at45db021b 15.2 main memory page read (opcode: d2h) 15.3 buffer read (opcode: d4h or d6h) 15.4 status register read (opcode: d7h) si 1 1 0 10 xxx cs so sck 12345 61 62 63 64 65 66 67 xx high-impedance d 7 d 6 d 5 data out command opcode msb t su t v d 4 68 si 1 1 0 10 xxx cs so sck 12345 37 38 39 40 41 42 43 xx high-impedance d 7 d 6 d 5 data out command opcode msb t su t v d 4 44 si 1 1 0 10 111 cs so sck 12345 78910 11 12 17 18 high-impedance d 7 d 6 d 5 status register output command opcode msb t su t v 6 d 4 d 0 d 7 lsb msb d 6
25 1937j?dflsh?9/05 at45db021b figure 15-1. algorithm for sequentially programming or reprogramming the entire array notes: 1. this type of algorithm is used for applications in which the entire array is programmed sequentially, filling the array page-by-page. 2. a page can be written using either a main memory page program operation or a buffer write operation followed by a buffer to main memory page program operation. 3. the algorithm above shows the programming of a single page. the algorithm will be repeated sequentially for each page within the entire array. start main memory page program through buffer (82h, 85h) end provide address and data buffer write (84h, 87h) buffer to main memory page program (83h, 86h)
26 1937j?dflsh?9/05 at45db021b figure 15-2. algorithm for randomly modifying data notes: 1. to preserve data integrity, each page of a dataflash sector must be updated/rewritten at least once within every 10,000 cumulative page erase/program operations. 2. a page address pointer must be maintained to indicate which page is to be rewritten. the auto page rewrite command must use the address specified by the page address pointer. 3. other algorithms can be used to rewrite portions of the flash array. low power applications may choose to wait until 10,000 cumulative page erase/program operations have accumulated before rewriting all pages of the sector. see application note an-4 (?using atmel?s serial dataflash?) for more details. start main memory page to buffer transfer (53h, 55h) increment page address pointer (2) auto page rewrite (2) (58h, 59h) end provide address of page to modify if planning to modify multiple bytes currently stored within a page of the flash array main memory page program through buffer (82h, 85h) buffer write (84h, 87h) buffer to main memory page program (83h, 86h) 16. sector addressing pa9 pa8 pa7 pa6 pa5 pa4 pa3 pa2 - pa0 sector 0000000 x 0 0 0xxxxx x 1 0 1xxxxx x 2 1xxxxxx x 3
27 1937j?dflsh?9/05 at45db021b 17. ordering information 17.1 standard package options f sck (mhz) i cc (ma) ordering code package operation range active standby 20 10 0.01 at45db021b-cc at45db021b-rc at45db021b-sc at45db021b-tc 9c1 28r 8s2 28t commercial (0 c to 70 c) 20 10 0.01 at45db021b-ci at45db021b-ri at45db021b-si at45db021b-ti 9c1 28r 8s2 28t industrial (-40 c to 85 c) 17.2 green package options (pb/halide-free/rohs compliant) f sck (mhz) i cc (ma) ordering code package operation range active standby 20 10 0.01 at45db021b-cu at45db021b-ru at45db021b-su AT45DB021B-TU 9c1 28r 8s2 28t industrial (-40 c to 85 c) package type 9c1 9-ball (3 x 3 array), 1.0 mm pitch, 5 x 5 mm plastic chip-scale ball grid array package (cbga) 28r 28-lead, 0.330" wide, plastic gull wing small outline package (soic) 8s2 8-lead, 0.210" wide, plastic gull wing small outline package (eiaj soic) 28t 28-lead, plastic thin small outline package (tsop)
28 1937j?dflsh?9/05 at45db021b 18. packaging information 18.1 9c1 ? cbga 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 9c1 , 9-ball (3 x 3 array), 5 x 5 x 1.2 mm body, 1.0 mm ball pitch chip-scale ball grid array package (cbga) a 9c1 04/11/01 dimensions in millimeters and (inches). controlling dimension: millimeters. a b c 32 1 2.0 (0.079) 1.50(0.059) ref 0.40 (0.016) dia ball typ 2.0 (0.079) 1.20(0.047)max 0.25(0.010)min 5.10(0.201) 1.00 (0.0394) bsc non-accumulative 4.90(0.193) 5.10(0.201) 4.90(0.193) 1.50(0.059) ref a1 id 1.00 (0.0394) bsc non-accumulative top view side view bottom view
29 1937j?dflsh?9/05 at45db021b 18.2 28r ? soic a 2. 3 9 ? 2.79 a1 0.050 ? 0. 3 56 d 1 8 .00 ? 1 8 .50 note 1 e 11.70 ? 12.50 e 1 8 .59 ? 8 .79 note 1 b 0. 3 56 ? 0.50 8 c 0.20 3 ? 0. 3 05 l 0.94 ? 1.27 e 1.27 typ pin 1 0o ~ 8 o 2 3 25 orch a rd p a rkw a y sa n jo s e, ca 951 3 1 title drawing no. r rev. 2 8 r, 2 8 -le a d, 0. 33 0" body width, pl as tic g u ll wing s m a ll o u tline ( s oic) c 2 8 r 5/1 8 /2004 common dimen s ion s (unit of me asu re = mm) s ymbol min nom max note a e c a 1 e 1 e d l b note: 1. dimen s ion s d a nd e1 do not incl u de mold fl as h or protr us ion. mold fl as h or protr us ion s h a ll not exceed 0.25 mm (0.010").
30 1937j?dflsh?9/05 at45db021b 18.3 8s2 ? eiaj soic 2 3 25 orch a rd p a rkw a y sa n jo s e, ca 951 3 1 title drawing no. r rev. 8s 2 , 8 -le a d, 0.209" body, pl as tic s m a ll o u tline p a ck a ge (eiaj) 10/7/0 3 8s 2 c common dimen s ion s (unit of me asu re = mm) s ymbol min nom max note note s : 1. thi s dr a wing i s for gener a l inform a tion only; refer to eiaj dr a wing edr-7 3 20 for a ddition a l inform a tion. 2. mi s m a tch of the u pper a nd lower die s a nd re s in bu rr s a re not incl u ded. 3 . it i s recommended th a t u pper a nd lower c a vitie s b e e qua l. if they a re different, the l a rger dimen s ion s h a ll b e reg a rded. 4. determine s the tr u e geometric po s ition. 5. v a l u e s b a nd c a pply to p b / s n s older pl a ted termin a l. the s t a nd a rd thickne ss of the s older l a yer s h a ll b e 0.010 +0.010/ ? 0.005 mm. a 1.70 2.16 a1 0.05 0.25 b 0. 3 5 0.4 8 5 c 0.15 0. 3 5 5 d 5.1 3 5. 3 5 e1 5.1 8 5.40 2, 3 e 7.70 8 .26 l 0.51 0. 8 5 ? 0 8 e 1.27 b s c 4 end view s ide view e b a a1 d e n 1 c e1 ? l top view
31 1937j?dflsh?9/05 at45db021b 18.4 28t ? tsop 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 28t , 28-lead (8 x 13.4 mm) plastic thin small outline package, type i (tsop) c 28t 12/06/02 pin 1 0o ~ 5o d1 d pin 1 identifier area b e e a a1 a2 c l gage plane seating plane l1 common dimensions (unit of measure = mm) symbol min nom max note notes: 1. this package conforms to jedec reference mo-183. 2. dimensions d1 and e do not include mold protrusion. allowable protrusion on e is 0.15 mm per side and on d1 is 0.25 mm per side. 3. lead coplanarity is 0.10 mm maximum. a ? ? 1.20 a1 0.05 ? 0.15 a2 0.90 1.00 1.05 d 13.20 13.40 13.60 d1 11.70 11.80 11.90 note 2 e 7.90 8.00 8.10 note 2 l 0.50 0.60 0.70 l1 0.25 basic b 0.17 0.22 0.27 c 0.10 ? 0.21 e 0.55 basic
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